{"id":293098,"date":"2025-04-29T09:12:17","date_gmt":"2025-04-29T09:12:17","guid":{"rendered":"https:\/\/news.talkwithrattan.com\/index.php\/2025\/04\/29\/mediatek-dimensity-9500-soc-may-offer-better-ray-tracing-ai-performance\/"},"modified":"2025-04-29T09:12:18","modified_gmt":"2025-04-29T09:12:18","slug":"mediatek-dimensity-9500-soc-may-offer-better-ray-tracing-ai-performance","status":"publish","type":"post","link":"https:\/\/news.talkwithrattan.com\/index.php\/2025\/04\/29\/mediatek-dimensity-9500-soc-may-offer-better-ray-tracing-ai-performance\/","title":{"rendered":"MediaTek Dimensity 9500 SoC May Offer Better Ray Tracing, AI Performance"},"content":{"rendered":"
\"MediaTek<\/div>


\n<\/p>\n

\n
\n

Dimensity 9500<\/a> SoC is rumoured to be in development as the latest flagship-tier smartphone processor from MediaTek. Ahead of its anticipated debut sometime later this year, a tipster suggests that it could be fabricated using TSMC’s N3P process (3nm). Powered by Arm’s latest Cortex-X9 series cores, the chipset is speculated to bring improvements related to ray tracing and artificial intelligence (AI<\/a>) \u2014 the latter supported by a neural processing unit (NPU) capable of delivering 100 tera operations per second (TOPS) performance.<\/p>\n

Tipster Digital Chat Station (translated from Chinese) leaked specifications of the purported MediaTek<\/a> Dimensity 9500 chipset in a post<\/a> on the Chinese microblogging platform Weibo. Fabricated using the N3P process, the SoC is tipped to come with an octa-core architecture, though its makeup could be different compared to what previous rumours suggested.<\/p>\n

Instead of having a 2 + 6 configuration, the Dimensity<\/a> 9500 chipset may have one Cortex-X930 prime cores dubbed \u201cTravis\u201d, three cores dubbed \u201cAlto\u201d, and four Cortex-A730 “Gelas” cores.<\/p>\n

The SoC is said to be complemented by an Immortalis-Drage GPU which could offer improvements in terms of ray tracing and AI, while also reducing the power consumption, courtesy of a new GPU microarchitecture. Meanwhile, an NPU 9.0 is tipped to deliver 100 TOPS of AI performance. As per the tipster, the Dimensity 9500 chipset will have 16MB of L3 cache and 10MB of SLC cache. Touted to be a flagship offering, it may support devices equipped with up to LPDDR5X RAM and up to UFS 4.1 storage.<\/p>\n

Past reports suggest that the N3P process used by TSMC for the purported chipset’s fabrication could result in a 5 percent performance gain and a 5-10 percent efficiency improvement as compared to the current Dimensity 9400 SoC which is built using the N3E process. It may also benefit from improved multi-thread performance with the use of Arm’s Scalable Matrix Extension (SME) which can accelerate AI and ML-based applications and provide enhanced support for matrix operations.<\/p>\n

Although no official details are known regarding the launch timeline of the Dimensity 9500 SoC, its predecessor was announced in October 2024, and the purported chip could also launch around the same time this year.<\/p>\n<\/div>\n

\n For the latest tech news<\/a> and reviews<\/a>, follow Gadgets 360 on X<\/a>, Facebook<\/a>, WhatsApp<\/a>, Threads<\/a> and Google News<\/a>. For the latest videos on gadgets and tech, subscribe to our YouTube channel<\/a>. If you want to know everything about top influencers, follow our in-house Who’sThat360<\/a> on Instagram<\/a> and YouTube<\/a>. <\/p>\n

\n
\n
\n <\/p>\n
<\/div>\n

Mastercard Partners OKX, Nuvei to Launch Payment Ecosystem for Stablecoins<\/span>
\n <\/a>\n <\/div>\n<\/div><\/div>\n